Method and device for testing the ESD resistance of a semiconductor component

ABSTRACT

To test the ESD resistance of a semiconductor component ( 1 ), for example of a NOS transistor, which can be used as an PSD protective element in a chip ( 2 ), a direct current characteristic of the semiconductor component ( 1 ) is monitored and the ESD resistance of the respective semiconductor component ( 1 ) is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component ( 1 ) at which an increased leakage current occurs in the non-conducting direction of the semiconductor component ( 1 ) can be monitored in operation of the semiconductor coponent ( 1 ) using an applied direct current (I o ) and the ESD resistance of the semiconductor component ( 1 ) inferred depending on a change in this direct current failure threshold.

[0001] The present invention relates to a method and a device fortesting the ESD resistance of a semiconductor component, in particularof an ESD protective element used in a chip to protect againstelectrostatic discharges.

[0002] Electrostatic discharges (‘electrostatic discharge’ or“electrostatic damage”, ESD) pose a major problem in the field ofintegrated circuits. MOS and CMOS (“Comlementary Metal OxideSemiconductor”) circuits in particular are very sensitive with regard tosurges at their inputs. The static charge of a human being can amount tomany kV, thus lying markedly above the critical gate oxide breakdownvoltage of MOS components, so that the static charge of a human beingalone can lead to the breakdown of the gate oxide of a MOS component.

[0003] Memory modules or chips must therefore be protected againstelectrostatic discharges (ESD) to prevent failure of the respective chipdue to handling, i.e. due to picking up or touching, or in operation.Monitoring of the ESD properties of a chip during production isextremely important here, as the ESD properties can often deterioratedrastically even in the event of slight changes or adjustments in thetechnology.

[0004] Hitherto, suitably equipped special ESD testing laboratories havebeen required to carry out ESD measurements of this kind. In much ESDtesting laboratories, an ESD protective element or active semiconductorcomponent used in the semiconductor product to be tested and connecteddirectly to a suitable pad is investigated with regard to its loadcapacity relative to ESD pulses. ESD pulses typically have a length of 1ns-100 ns and a strength of several amperes and have a special pulseshape. ESD pulses of this kind can only be generated by special andtherefore expensive testing devices, considerable know-how also beingrequired to carry out such ESD measurements These ESD measurements havetherefore only taken place up to now in suitably designed centraldepartments or ESD testing laboratories, but not in the factory during aproduction or PCM (“Process Control Monitor”) test.

[0005] As well as the problems described above, a further disadvantageconsists in the fact that conventionally such ESD measurements arenormally only initiated following the failure of a relevant chip productfor the customer, owing to the outlay associated with these. Actualmonitoring of the process at regular intervals does not take place. Inaddition, the ESD testing devices used in such ESD testing laboratoriesare not designed for a high throughput, so that statistical reportsregarding the occurrence of faults owing to electrostatic discharges areonly obtainable to a very limited degree and only with a great timeloss. It thus takes a very long time after a fault has been establishedto restore the ESD resistance of the manufacturing processes of suitablechips.

[0006] The object of the present invention therefore is to provide amethod and a device for testing the ESD resistance of a semiconductorcomponent, using which the ESD resistance can be tested in particular inthe simplest manner possible even during the production process.

[0007] This object is achieved according to the invention by a methodwith the features of claim 1 and a device with the features of claim 9.The sub-claims define preferred and advantageous embodiments of thepresent invention.

[0008] The present invention is based on the realization that changes inthe ESD resistance are generally also reflected in special aspects ofthe direct current characteristic of the respective semiconductorcomponent. Direct current here is taken to mean all currents with pulselengths that are many times greater than ESD pulses (with a pulse lengthof approx. 1 ns-100 ns), i.e. with pulse lengths in particular greaterthan 1 μs. Investigations have shown that a reduced resistance of a MOStransistor, for example, when loaded with short ESD pulses isaccompanied by a reduced resistance to direct current loading, i.e. thedirect current characteristic or the direct current characteristic curveof the respective component correlates to its ESD resistance.

[0009] To test the ESD resistance of a semiconductor component, it istherefore proposed according to the invention to monitor the directcurrent characteristic of this component and to infer the ESD resistanceof the relevant component depending on this.

[0010] To determine the ESD resistance, it is proposed in particular toascertain the direct current failure threshold of the respectivesemiconductor component that is present when the component is operatedusing an applied direct current, it being possible to assume in theevent of a change in this direct current failure threshold that the ESDperformance, i.e. ESD resistance, is also impaired. In this case thedirect current failure threshold is defined as the value of the directcurrent applied at which the respective semiconductor comonent has anincreased leakage current in the non-conducting direction compared witha set threshold value.

[0011] One particular advantage connected with the present inventionconsists in the fact that the direct current measurement proposedaccording to the invention for testing the ESD resistance can also becarried out in the factory, i.e. during production, using standardcurrent sources available there and without any particular specialistknowledge. If the ESD protective elements of the chips that are to betested with regard to their ESD resistance are dimensioned to a gatewidth of approx. 2-20 μm in CMOS technologies, the direct currentfailure threshold can be set to a value that is attained with standardPCM testers (typically 0.1A). Due to this, measurement of the ESD ordirect current resistance can be implemented even in conventionalstandard PCM programmes and up to 100% monitoring of all wafers producedcan be achieved virtually without any additional expenditure.

[0012] In addition, it is advantageous that excellent statisticalreports can be obtained regarding the ESD fault frequency using simplemeans. Even ESD failures that only occur with a low level of probabilityare thus detected.

[0013] Dramatically accelerated learning cycles with regard to ESDproblems constitute a further decisive improvement compared with theconventional procedure described at the beginning. Whereas according tothe prior art all ESD measurements have to be carried out in special ESDtesting laboratories with a low throughput, the present invention makesit possible for all the information required to be extracted henceforthextremely quickly on the spot from an inspection test that is carriedout anyway and thus for it to be able to be incorporated immediatelyinto the manufacturing process.

[0014] The present invention is explained in greater detail below withreference to a preferred embodiment and to the enclosed drawing.

[0015] The sole diagram shows a strongly simplified diagrammaticrepresentation of a device for testing the ESD resistance of asemiconductor component according to a preferred embodiment of thepresent invention.

[0016] The basis of the present invention is the realization thatchanges in the ESD resistance of a semiconductor component are generallyreflected also in special aspects of the direct current characteristicof this semiconductor component.

[0017] The diagram shows a MOS transistor as an example, a similar formof which (e.g. varied in size) is used as an ESD protective element 1 ina chip 2. The ESD resistance of this ESD protective element should beable to be tested if possible during production of the chip 2, i.e.while still in the factory. This is facilitated with the aid of thepresent invention in that the direct current characteristic of the ESDprotective element 1 is monitored and the ESD resistance of this ESDprotective element 1 and semiconductor component is inferred dependingon this.

[0018] To test the ESD resistance, a testing device 3 is provided, whichhas a current source 4 for applying direct current I_(o) to the ESDprotective element 1. Furthermore, the testing device 3 has a measuringdevice 5, which measures a direct current characteristic of the ESDprotective element 1 that appears as a result of this. The measuringdevice 5 controls the current source 4 here in particular such that thedirect current I_(o) applied is increased continuously util a certainfailure threshold can be determined by the measuring device 5 withreference to the direct current load. Direct current failure is assumedhere in particular if the ESD protective element 1 has an increasedleakage current I_(L) in the non-conducting direction. By evaluating theleakage current of the ASD protective element 1 in the non-conductingdirection, an evaluation device 6 contained in the testing device 3 caninfer the momentary direct current failure threshold of the ESDprotective element 1. By comparing the determined direct current failurethreshold of the ESD protective element 1 with the value of the directcurrent failure threshold of a fault-free ESD protective element 1, theevaluation device 6 can now establish whether any change, i.e. anydeterioration, is present in the direct current failure threshold of theESD protective element, it being possible to assume in this case thatthe ESD performance, i.e. the ESD resistance, of the ESD protectiveelement 1 is also impaired.

[0019] To determine the ESD resistance of the ESD protective element 1,it is not absolutely necessary for the direct current failure thresholdof the ESD protective element 1 tested to be determined as describedabove. Instead of this, a previously defined direct current I_(o) canalso be applied to the ESD protective element 1 to be tested by thetesting device 3, no damage to the relevant semiconductor componentnormally occurring with this direct current I_(o) if the component hasthe required ASD resistance. If the measuring device 5 and evaluationdevice 6 now detect a leakage current I_(L) of the ESD protectiveelement 1 in the non-conducting direction that is increased comparedwith a set threshold value at this direct current value I_(o), theevaluation device 6 infers accordingly that the ESD resistance of theESD protective element 1 is also impaired.

[0020] The method described above is particularly advantageous if theESD protective element used in a chip 2 is scaled to a gate width ofapprox. 2-20 μm and used on the wafer at a point that is favourable formonitoring purposes, e.g. in the PCM framework (“Process ControlMonitor”), so that the direct current failure threshold to be monitoredcan be set to a value that can be attained with standard PCM testers.The direct current failure threshold can be adapted in this way toexisting testing devices, i.e. the present invention can even beimplemented in standard PCM programmes, so that 100% monitoring of allchips 2 or wafers produced can be achieved virtually without anyadditional expenditure.

1. Method for testing the ESD resistance of a semiconductor component,characterized in that a direct current characteristic of thesemiconductor component (1) is monitored and the ESD resistance of thesemiconductor component (1) is inferred depending on this.
 2. Methodaccording to claim 1, characterized in that a direct current failurethreshold of the semiconductor component (1) at which a failure of thesemiconductor component (1) occurs in direct current operation of thesemiconductor component (1) is monitored and the ESD resistance of thesemiconductor component is inferred depending on this.
 3. Methodaccording to claim 2, characterized in that the direct current failurethreshold is defined as a direct current (I_(o)) at which thesemiconductor component (1) has a leakage current (I_(L)) in thenon-conducting direction that is increased compared with a predeterminedthreshold value.
 4. Method according to claim 2 or 3, characterized inthat to monitor the direct current failure threshold of thesemiconductor component (1), the semiconductor component is operatedusing an aplied direct current (I_(o)).
 5. Method according to claim 4,characterized in that the direct current failure threshold of thesemiconductor component (1) is determined in that the applied directcurrent (I_(o)) with which the semiconductor component (1) is operatedis increased until the leakage current (I_(L)) of the semiconductorcomponent (1) has exceeded the set threshold value in the non-conductingdirection.
 6. Method according to one of the preceding claims,characterized in that the method is used for testing the ESD resistanceof a MOS component with a gate width of 2-20 μm.
 7. Method according toclaim 6, characterized in that the method is used for testing the ESDresistance of a MOS component (1) used as an ESD protective element in asemiconductor chip (2) formed in CMOS technology.
 8. Method according toone of the preceding claims, characterized in that to monitor the directcurrent characteristic, the semiconductor component (1) is operatedusing a current with a pulse length greater than 1 μs.
 9. Device fortesting the BSD resistance of a semiconductor component (1), with ameasuring device (5) for measuring a direct current characteristic ofthe semiconductor component (1), and with an evaluation device (6) forassessing the ESD resistance of the semiconductor component (1)depending on the direct current characteristic of the semiconductorcomponent (1) measured by the measuring device (5).
 10. Device accordingto claim 9, characterized in that the measuring device (5) is designedso that it detects a direct current failure threshold of thesemiconductor component (1) at which failure of the semiconductorcomponent (1) occurs in direct current operation.
 11. Device accordingto claim 10, characterized in that the measuring device (5) is designedsuch that to measure the direct current failure threshold of thesemiconductor component (1) it operates the semiconductor component (1)using an applied direct current (I_(o)) and detects as the directcurrent failure threshold that direct current value at which a leakagecurrent (I_(L)) that is increased compared with a set threshold valueoccurs at the semiconductor component (1) in the non-conductingdirection.
 12. Device according to claim 10 or 11, characterized in thatthe evaluation device (6) is designed such that it infers deficient ESDresistance of the semiconductor component (1) if a direct currentfailure threshold that is reduced compared with a predetermined directcurrent failure threshold has been detected by the measuring device (5).13. Device according to one of claims 9-12, characterized in that thedevice for executing the method is designed according to one of claims1-8.